How to organize configuration objects in UVM Testbenches?

Some of the observations about the Complex Verification Environments
   1. Verification Environment will generally have a number of agents (or UVCs).
   2. Testbench will have different modes and configurations at the top level
   3. Agents will have different configurations and randomizations to play with.

Its indeed a laborious task of keeping track of these configurations if not planned and organized properly. There is a need to structure the configurations in an intuitive way so that it not only helps the Verification Team collaborate better but also easy to sustain the Verification Environment.

Following is suggested by UVM user guide:-
1. Each agent should have all the agent level configurations captured in a configuration object (uvm_object)
 2. Environment will have a config object for the environment level or chip level.

                                   Picture Courtesy- Accellera

That sounds pretty straight-forward to understand and implement. However the main aim of the providing configuration objects is to allow the test (or testcase writer) to control/configure the fields in the configuration objects to achieve the test goal or to create various scenarios of interest. This requires some scheme to organize the config objects.

What is the scheme for handling various config objects in the environment?
As we know, Agents' config objects are generally in compliation scope of that particular agent as follows:-

                                                  Fig2. abc_pkg



In order to keep the configuration objects organized in a structured way, and still allow the test writer to intuitively use the config objects, following scheme is devised. The scheme is illustrated using the following piece of code.

      Fig3. Illustration of scheme for handling config objects in UVM testbench

Also, the env_config is instantiated in the test, test writer can access the env_config and agent level configs hierarchically to control the configurations of testbench.

What are the Advantages?

1.  Easy and intuitive way of accessing configurations information not only for Test writers but also design engineers/managers to review the configurations. Review of configuration capabilities of the testbench is very important because this drives the verification and its goals
2. Environment config contains only the pointers to the agent level configs and actual config object of a given agent resides within the compilation scope of that agent. Thus, Agent are kept pretty independent and they don't access environment level config object and hence agent can be reused across different environment with almost no change required.
3. Tests access the agent level config through environment level config object and hence all the configurations done in the testcase are streamlined and this makes the testcases easy to understand.

Clock Generation with jitter

System Verilog Code:-

//---------------------------------------------------------------------------------------
// Name: jitter_clock_gen
// Author: Bharath Kumar Y
// Description: This module will generate a clock with
//              period                = 16ps
//              Max Skew/half clock   = +/-1ps
//              Max Skew/clock period = +/-2ps
// Copyright (C) Bharath Kumar Y
//----------------------------------------------------------------------------------------

`timescale 1ps/1ps

module jitter_clock_gen;
//Initializations
  bit req0=0;
  bit clk=0;
  integer seed;
  real zero_time=0;
  real one_time=8;


// Just to run the sim for some good amount of time to get
// enough clock edges
initial begin
  # 100 $finish;
end

// Actual clock generation clock
always
  #(8+$dist_uniform(seed,-1,1)) clk = ~clk;

// Checking of clock geneation implemented using
// Immediate assertions
// This block will assert errors when the
// half clock period != 8
always @* 
begin
  if(clk==0) begin
    req0=1;
    zero_time = $realtime;
    $display("zero_time = %t",$realtime);
    assert(!(($realtime<(one_time+8))));
    assert(!(($realtime>(one_time+8))));
  end

  if (req0==1 && clk==1) begin
    req0=0;
    one_time=$realtime;
    $display("time:%t:-req0=%b,req=%b",$realtime,req0,clk);
    assert(!(($realtime<(zero_time+8))));
    assert(!(($realtime>(zero_time+8))));
  end
end

endmodule

Output for the same code using ncsim:-

ncsim> run
zero_time =                   15
ncsim: *E,ASRTST (./fun1.sv,41): (time 15 PS) Assertion jitter_clock_gen.__assert_1 has failed
time:                  22:-req0=0,req=1
ncsim: *E,ASRTST (./fun1.sv,49): (time 22 PS) Assertion jitter_clock_gen.__assert_3 has failed
zero_time =                   29
ncsim: *E,ASRTST (./fun1.sv,41): (time 29 PS) Assertion jitter_clock_gen.__assert_1 has failed
time:                  37:-req0=0,req=1
zero_time =                   46
ncsim: *E,ASRTST (./fun1.sv,42): (time 46 PS) Assertion jitter_clock_gen.__assert_2 has failed
time:                  53:-req0=0,req=1
ncsim: *E,ASRTST (./fun1.sv,49): (time 53 PS) Assertion jitter_clock_gen.__assert_3 has failed
zero_time =                   60
ncsim: *E,ASRTST (./fun1.sv,41): (time 60 PS) Assertion jitter_clock_gen.__assert_1 has failed
time:                  68:-req0=0,req=1
zero_time =                   76
time:                  85:-req0=0,req=1
ncsim: *E,ASRTST (./fun1.sv,50): (time 85 PS) Assertion jitter_clock_gen.__assert_4 has failed
zero_time =                   93
Simulation complete via $finish(1) at time 100 PS + 0
./fun1.sv:26   # 100 $finish;

UVM Ports - Illustrated

There is always this question as to when to use uvm_analysis_port, uvm_analysis_export and uvm_analysis_import

The below diagram illustrates the correct use of all types of ports mentioned above through the 'Stacked UVCs' example.  This diagram illustrates the connection of BOTTOM UVC's monitors with the monitors of TOP UVCs. 

The requirement here is that any of the BOTTOM UVCs can be connected to any of the TOP UVCs. This means that we need to have a router component with uvm_analysis_exports since only exports can forward the data coming from the source 'port's of BOTTOM UVC's monitors. BOTTOM UVC's Monitor is the originator of the transacation and hence its required to have the uvm_analysis_port.

Monitors of the TOP UVCs are supposed to have the uvm_analysis_imports as they are the ultimate consumers of the transactions

UVM Questions - 6

                                               Courtesy - Paradigm Works Inc

 Q:  Why there should be a seperate sequencer and driver in an UVM agent?
                                              OR
 Q:  Why UVM doesn't have single component which combines Driver and Sequencer?


Firstly,
     Typically if you are dealing with a packet/frame with layered architecture where lower layer level data encapsulate the higher layer level data. In this case its better to architect the UVC in a layered way.  This renders the testbench modular and facilitates the easy reusability and parallel development of Testbench.
    Once we do the layered architecture of UVCs, only Bottom UVCs need to have Driver since its attached to the DUT interface, higher leayer UVCs don't need to have driver since they don't attach to any DUT interface instead they attach to the bottom UVCs. Higher layer sequences in the sequencer interact with to the lower level UVCs through sequence item as shown in the above diagram.

Secondly,
     At the SoC level verification environment, its often required to use the virutal sequences to sequence/bypass the lower level sequences

                                   Courtesy - Accellera UVM1.1 User guide

As per the guide,

     There are three ways in which the virtual sequencer can interact with its  subsequencers:
a) “Business as usual”—Virtual subsequencers and subsequencers send transactions simultaneously.
b) Disable subsequencers—Virtual sequencer is the only one driving.
c) Using grab() and ungrab()—Virtual sequencer takes control of the underlying driver(s) for a limited time

(b) and (c) makes the separation of sequencer and driver obvious and hence they are independent components in UVM. Without this seperation, its difficult for virtual sequencer to grab the control of the underlying drivers and achieve interesting scenarios at the SoC/full chip level testbench.

UVM Questions - 5

Q. In the accellera's UVM User guide, there are two monitors shown one at the agent level and another at the environment level, why ?

                                     Picture Courtesy- Accellera


A: There are variety of reasons why you need Monitor at different levels

    Any agent monitor also has a collector inside which collects only that data from DUT interfaces and forms a transaction which is destined to that particular agent.  As shown in the above diagram, Monitor will also have a UVM analysis ports to pass the transaction to other components in the environment like Scoreboard.

   However, the Monitor at the environment level (called as 'bus monitor' here) also snoops the DUT interface and forms the transactions destined to any master/slave agent on the bus but it won't pass the transactions to other components of the environment like scoreboard. This bus-level monitor uses those transactions to perform checking and coverage for the activities that are not necessarily related to a single agent.

Bus monitor is very useful for debugging at the SOC top level testbench environment where both source and destination of data flow (transactions) are within DUT itself. 

UVM Questions - 4

Q: What is the difference between uvm_component and uvm_object?
                       OR
Q: We already have uvm_object, why do we need uvm_component which is actually derived class of uvm_object?

A: uvm_component is a static entity and always tied(bind) to a given hardware and/or a TLM interface
 
   uvm_object is a dynamic entity and is not tied to any hardware/TLM interface

   uvm_component like uvm_driver is always connected to a particular DUT interface because throughout the simulation its job is fixed i.e. to drive the designated signals into DUT

   uvm_object like uvm_transaction is not connected to any particular DUT interface and its fields can take any random value based on randomization constraints.
 
   Though uvm_component is derived from uvm_object, uvm_component has got these additional interfaces

       * Hierarchy provides methods for searching and traversing the component hierarchy.
       * Phasing defines a phased test flow that all components follow, with a group of standard phase methods and an API for custom phases and multiple independent phasing domains to mirror DUT behavior e.g. power
       * Configuration provides methods for configuring component topology and other parameters ahead of and during component construction.
       * Reporting provides a convenience interface to the uvm_report_handler.  All messages, warnings, and errors are processed through this interface.
       * Transaction recording provides methods for recording the transactions produced or consumed by the component to a transaction database (vendor specific).
        * Factory provides a convenience interface to the uvm_factory. The factory is used to create new components and other objects based on type-wide and instance-specific configuration

Acronyms used:-
DUT - Design Under Test
TLM - Transaction Level Modelling
API - Application Programming Intefaces

UVM Questions - 3

Q. What is the advantage of using type_id::create() over new() while creating objects ?

There is nothing wrong in creating the objects for any uvm_component with constructor function new(), however if you are using UVM, there are some advantages of using factory way of creating objects i.e using

classname ::type_id::create("object name", parent)

This is what UVM1.1 Class Reference says

"Using the factory instead of allocating them directly (via new) allows different objects to be substituted for the original without modifying the requesting class"


Q: How to implement polymorphism in UVM?

The above advantage is illustrated through the polymorphism of a 'generic monitor' as follows:-

Any generic Monitor component's implementation will be

   class xyz_monitor extends uvm_monitor ;

      task run_phase ;

         // Implements monitor functionality here

      endtask

   endclass

Monitor has following modes of operation apart from basic xyz_monitor mode

     1. Mode1

     2. Mode2

   class monitor_mode1 extends xyz_monitor;

     // Implement monitor mode1

   endclass

   class monitor_mode2 extends xyz_monitor;

     // Implement monitor mode2

   endclass

    class parent extends uvm_env;

         .....

         ....

         xyz_monitor mon;

        mon = xyz_monitor::type_id::create("mon",this);

    endclass

Now during compilation you can specify which mode of the monitor you need for a particular simulation run using

    +uvm_set_type_override=<\req_type\>, <\overrid_type\>[,<\replace\>]

which work like the name based overrides in the factory--factory.set_type_override_by_name()

For the above example, If we need mode1 of monitor then the command line will be
    +uvm_set_type_override=xyz_monitor,monitor_mode1

For mode2, it would be
    +uvm_set_type_override=xyz_monitor,monitor_mode2

Effectively, there were no exclusive objects created for monitor mode1 or mode2, it basically override the object created for the object 'mon' which was originally of type 'xyz_monitor' and this is called Polymorphism because 'mon' object can potentially be any one of these types i.e. xyz_monitor or monitor_mode1 or monitor_mode2 for a given simulation run.

In fact, for the same monitor example if we have two instances(or objects) of xyz_monitor in your environment

    class parent extends uvm_env;

         .....

         ....

         xyz_monitor mon;

         xyz_monitor mon_extra;

        mon           = xyz_monitor::type_id::create("mon",this);

        mon_extra = xyz_monitor::type_id::create("mon",this);

    endclass

Now during compilation(command line) you can specify which modes of the monitor you need for a particular simulation run using
 +uvm_set_inst_override=<\req_type\>,<\overrid_type\>,<\full_inst_path\>

We can override 'mon' object to be of type monitor_mode1 using
 +uvm_set_inst_override=xyz_monitor,monitor_mode1,uvm_test_top.env.mon

We can override 'mon_extra' object to be of type monitor_mode2 using
 +uvm_set_inst_override=xyz_monitor,monitor_mode2,uvm_test_top.env.mon_extra

Please note that for 'uvm_set_inst_overrride', you need extra argument which is the path of 'object' and it has to start from uvm_test_top