learn-verification

Here I am going to blog about the practical as well as theoritical issues that today's ASIC verification engineer faces.

Monday, April 14, 2014

How to organize configuration objects in UVM Testbenches?

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Some of the observations about the Complex Verification Environments    1. Verification Environment will generally have a number of agents...
2 comments:
Thursday, February 28, 2013

Clock Generation with jitter

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System Verilog Code:- //--------------------------------------------------------------------------------------- // Name: jitter_clock_ge...
1 comment:
Wednesday, February 27, 2013

UVM Ports - Illustrated

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There is always this question as to when to use uvm_analysis_port, uvm_analysis_export and uvm_analysis_import The below diagram illustr...
2 comments:
Monday, February 11, 2013

UVM Questions - 6

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                                               Courtesy - Paradigm Works Inc  Q:  Why there should be a seperate sequence...
1 comment:
Wednesday, December 12, 2012

UVM Questions - 5

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Q. In the accellera's UVM User guide , there are two monitors shown one at the agent level and another at the environment level, why ? ...

UVM Questions - 4

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Q: What is the difference between uvm_component and uvm_object?                        OR Q: We already have uvm_object, why do we need uvm...
1 comment:
Friday, December 7, 2012

UVM Questions - 3

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Q. What is the advantage of using type_id::create() over new() while creating objects ? There is nothing wrong in creating the objects fo...
11 comments:
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