I was initially not so concerned about this topic, but as I travelled enough as ASIC verification engineer, I started realising that this(mindset of verification engineer) means a lot.
Why is it so important? If verification guy can't, there is a high chance that nobody will reach that bug's territory. verification is the right guy because he has the right arsenal to go and attack it.
Verification Engineer should have following traits
1. Attention to design details
2. Double checking on checkers' implementation
3. Always aware of simulation performance
4. Not getting biased by Designer's colorful talks
5. Express Doubt every bit of design.
6. Ask questions like how do I improve my verification environment